July 19, 2026 • 2 hours
M.tech, BITS, Pilani
FPGAs are widely used in space, aerospace, and defense systems for mission-critical control, communication, and on-board processing tasks. However, radiation effects such as Single Event Upsets (SEUs), Single Event Transients (SETs), and configuration memory corruption pose a significant challenge to FPGA reliability. This hands-on tutorial presents practical RTL-level techniques to harden FPGA designs against radiation, focusing on methods that engineers can directly implement and verify. Participants will gain insight into TMR, safe FSM design, error detection and correction (EDAC), temporal redundancy, and configuration memory protection. Through RTL simulation and live demonstration, attendees will see fault injection and mitigation in action, understanding the impact of radiation-induced errors and how hardened designs recover automatically. The session also introduces verification best practices, including fault injection strategies and radiation-aware testing. By the end of the tutorial, participants will have actionable templates and a clear methodology to develop and validate robust FPGA designs for SPACE applications.
M.tech, BITS, Pilani
Hariprasad Bhat is a seasoned professional with over 13 years of rich experience in RTL Design & FPGA implementation domain, seamlessly blending this expertise with hands-on embedded hardware design skills His extensive career spans protocol-specific RTL IP development, hardware schematic design, and system bring-up activities. At Lekha Wireless, Hariprasad played a pivotal role in developing wireless radio technology for defense and avionics applications. Following the merger, he now leads the RTL design–FPGA implementation team at CoreEL Technologies in Bengaluru, building reliable and robust wireless communication systems. Prior to his tenure at CoreEL Tech, Hariprasad contributed significantly to iWave Systems for over half a decade. During this time, he gained comprehensive exposure to advanced communication protocols such as USB3, DisplayPort, HDMI and PCIe Gen3, among others. Additionally, he served at Granite River Labs, where he was instrumental in defining the architecture of the USB4 compliance solution. Beyond his professional endeavors, Hariprasad is an active volunteer and serves as an Executive Committee member of the IEEE CAS Bangalore Society. As a senior IEEE member, he frequently contributes to workshops aimed at enhancing the skills of young professionals in the VLSI domain. Currently, he is the Vice-chair, IEEE CAS, Bangalore section. Hariprasad holds a BE (E&C) degree from Srinivas Institute of Technology, Mangalore, graduating in 2012. Currently, pursuing MTech in VLSI & Microelectronics from BITS, Pilani.
FPGA designers, system architects, and engineers in space, aerospace, and defense sectors seeking practical, deployable techniques for radiation-tolerant RTL design.
Contact:
Mohit Kumar
M: +91 741 178 8569
E: mohit@cimglobal.net
